1. Field of the Invention
The present invention relates to a semiconductor memory device which can write and read data in random sequence, and more particularly, it relates to a BiMOS semiconductor memory device including bipolar transistors and insulated gate field effect transistors (MOS transistors) as its components. More specifically, the present invention relates to a static random access memory (SRAM) having a BiCMOS structure, which requires no refresh operation.
2. Description of the Related Art
A static random access memory (hereinafter simply referred to as SRAM) can be accessed at a high speed, since SRAM requires no RAS precharge time for precharging bit lines and no RAS-CAS delay time resulting from address multiplexing, dissimilarly to a DRAM (dynamic random access memory). Further, an access time for such an SRAM can be reduced as compared with that for a DRAM since memory cells of the SRAM are in flip-flop structures so that data are read in a non-destructive manner dissimilarly to the DRAM employing capacitors and hence it is not necessary to restore the head data and to employ latch type sense amplifiers.
Due to the aforementioned characteristics, an SRAM is widely applied to a high-speed cash memory or the like, which requires high-speed operability.
While the SRAM has a short access time, each memory cell provided therein requires four transistors in total including two transistors for forming a flip-flop and access transistors for transmitting memory cell data to bit lines, as well as a resistive element (circuit element such as a high resistance load or a TFT) for pulling up a latch node of the flip-flop. Thus, occupied areas of the memory cells are increased as compared with those of DRAM memory cells, each of which consists of only a single transistor and a single capacitor. Therefore, the cost per bit of the SRAM is higher than that of the DRAM.
With development in a technique of improving the degree of integration of such an SRAM, however, there have recently been proposed various types of highly integrated mass storage SRAMs. These SRAMs employ various structures for high integration, stable operations and high-speed operations.
A principal object of the present invention is to provide an improved SRAM, which stably operates at a high speed in a novel structure.
An SRAM is provided with a lad circuit for pulling up (precharging) each bit line potential to a supply potential Vcc level. This bit line load circuit reduces the amplitude of the bit line potential in data reading, thereby increasing the speed of data reading.
The SRAM has no RAS precharge period, dissimilarly to a DRAM. Therefore, it is possible to execute data read and write operations by continuously accessing the SRAM with no intervals. In data writing, a write driver discharges the potential of one of a selected pair of bit lines from the precharge level of the Vcc level to a ground potential GND level. After completion of the write operation, the bit line potential which is discharged to the ground potential level is again charged to the supply potential Vcc level by the bit line load circuit.
When a word line is selected before the bit line potential is sufficiently recovered in a data read operation which is executed following the data write operation, this leads to erroneous data writing in the selected memory cell or delay of a data read time, since the time required for changing the bit line potential to a potential corresponding to the read data is increased. In order to reduce the access time, therefore, it is necessary to pull up the bit line potential at a high speed after completion of the data writing. Japanese Patent Laying-Open No. 3-29189 (1991) discloses an exemplary structure for solving the problem of "write recovery", i.e., recovery of a bit line potential after completion of a data write operation.
In the technique described in Japanese Patent Laying-Open No. 3-29189 (1991), an output of a write driver is set at a high level after completion of data writing so that the write driver is connected to a bit line for a prescribed period after completion of the writing, to precharge the bit line by both of a bit line load circuit and the write driver. However, the "write recovery" cannot be regarded as efficient since the bit line potential is pulled up to a supply potential Vcc level and it takes time to equalize the bit line potential.
Japanese Patent Laying-Open No. 63-211190 (1988) discloses a structure of inhibiting a bit line load circuit from a bit line charging operation in operation of a data read sense amplifier and starting the bit line charging operation of the bit line load circuit after completion of the sense amplifier operation for precharging the bit line. However, this technique is related to only bit line precharging in data reading, and no "write recovery" is taken into consideration.
Japanese Patent Laying-Open No. 2-91886 (1990) discloses a structure of forming a bit line load circuit for precharging a bit line by a bipolar transistor and an insulated gate field effect transistor (hereinafter simply referred to as a MOS transistor) for increasing the speed for precharging the bit line. However, this technique is also insufficient in consideration of high-speed access, since the bit line is precharged to a supply potential Vcc level.
Accordingly, a specific object of the present invention is to provide a structure which can sufficiently increase a margin for "write recovery".
An SRAM employs a differential amplifier type sense amplifier utilizing a constant current source as a sense amplifier for data reading. This differential amplifier type sense amplifier is adapted to read a slight potential difference between bit lines at a high speed while exerting no influence on the bit line potentials. In general, a memory cell array of an SRAM is divided into blocks so that an output of a sense amplifier which is provided in correspondence to a selected block is transmitted to an internal data bus. In this case, the output of the sense amplifier is generally transmitted to the internal data bus through an emitter-follower transistor. An emitter of the emitter-follower transistor is connected to the internal data bus in common, Japanese Patent Laying-Open No. 3-66095 (1991) discloses an example of such a structure.
According to this technique, a clamp circuit is provided for bringing bases and emitters of emitter-follower transistors which are provided for nonselected sense amplifiers into reverse bias states, thereby guaranteeing transmission of low-level data in emitter-coupled logic to the internal data bus. However, this literature is merely aimed at reliably reading low-level data, and no increase in speed in the sense operation is taken into consideration.
Accordingly, another specific object of the present invention is to provide a structure which can read data at a high speed.
A differential amplifying stage of a sense amplifier provided in an SRAM utilizes a constant current source. This constant current source includes a transistor element which receives a reference voltage in its control electrode (a base of a bipolar transistor or a control gate of a MOS transistor). A current which is supplied by the constant current source decides the output voltage level of the differential amplifying stage. In order to correctly read data, it is necessary to set the output voltage level of the differential amplifying stage at a correct value. Thus, the current which is supplied by the constant current source must be at a constant level. In other words, it is necessary to set the reference voltage which is employed for generating the constant current correctly at a predetermined level.
A DRAM utilizes a structure of trimming an internal down-converted voltage by laser-blowing resistances which are arranged in parallel with each other for generating the internal stepdown voltage (refer to Japanese Patent Laying-Open No. 4-102300 (1992)). However, this prior art is related to a DRAM and aimed at no application to a constant current source for a sense amplifier of an SRAM, and describes no structure which can easily monitor whether or not a differential amplifying stage of a sense amplifier has prescribed operation characteristics in the exterior by a reference voltage generated by a reference voltage source.
Accordingly, still another specific object of the present invention is to provide a structure which can set a reference voltage employed for a reference current source correctly at a prescribed value and which can easily monitor the reference voltage in the exterior.
In a semiconductor memory device, a block structure of driving only a selected block is employed in consideration of reduction in power consumption. A single block includes a plurality of I/O blocks corresponding to a plurality of data input/output pins respectively. In consideration of high integration and the yield of an SRAM, it is necessary to efficiently repair defective memory cells. In relation to a system for repairing a defective memory cell, known is a "shift redundancy circuit" of simply shifting a target for connecting a column decoder output node dissimilarly to a system of replacing a defective bit line by a dedicated spare column.
In the structure of such a "shift redundancy circuit", however, defective memory cells are generally independently repaired in each I/O block. In a single memory block, therefore, a "spare column (redundant column)" is present in correspondence to each I/O block. When only on I/O block has a defective memory cell in a single memory block, there remains unused "spare columns" in this memory block. Thus, the "spare columns" are inferior in utilization factor and the memory cell array is reduced in degree of integration.
Accordingly, a further specific object of the present invention is to provide a shift redundancy circuit which can efficiently repair a defective memory cell in a single memory block.
In an SRAM, further, an output buffer is generally provided with no specific protective circuit since an output transistor which is the final stage of the output buffer has sufficient electrostatic breakdown resistance itself. In general, a recent SRAM has an interface which is compatible with TTL or LVTTL. TTL has VIH (input high level) of 2.2 V, VIL (input low level) of 0.8, VOH (output high level) of 2.4 V and VOL (output low level) of 0.4 V. LVTTL has VIH and VIL of 2.0 V and 0.8 V, and VOH and VOL of 2.4 V and 0.4 V respectively. The TTL and the LVTTL are different in quantity of current in signal output from each other.
In a two-power source system including an SRAM having an operating supply voltage Vcc of 3.3 V and a CPU, serving as an external processing unit, having an operating supply voltage Vcc of 5 V, the operating supply voltage of the CPU serving as an external processing unit may destruct components forming an output buffer of the SRAM. In relation to an integrated circuit device having a CMOS structure, known is a structure of providing a protective resistance and a protective diode to an input buffer (refer to Japanese Patent Laying-Open Nos. 60-224259 (1985), 63-37646 (1988) and 3-9559 (1991)). However, no consideration is made on a protective circuit with respect to an abnormal voltage for an output buffer in a BiMOS-SRAM.
Accordingly, a further specific object of the present invention is to provide a BiMOS-SRAM comprising a highly reliable output buffer.
In a battery driving system employing a battery as a power source, an operating supply voltage Vcc fluctuates with time. On the other hand, a supply voltage nay accidentally fluctuate in a computer system which is provided with a number of memories. In general, an input buffer has a CMOS inverter structure. An input logic threshold value of the input buffer is varied with the level of the supply voltage Vcc. Even if a response time (time required for ascertaining the level of an output signal) of the input buffer for an input signal which rises from a low level to a high level is equalized to a response time for an input signal which falls from a high level to a low level with respect to a certain supply voltage level, therefore, these response times are made different from each other following fluctuation of the operating supply voltage Vcc. Thus, it is impossible to guarantee a correct operation.
Accordingly, a further specific object of the present invention is to provide an input buffer having input/output characteristics which are not dependent on a supply voltage.